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93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.4
Erase
The DO pin indicates the Ready/ Busy status of the
device if CS is brought high after a minimum of 250 ns
The ERASE instruction forces all data bits of the speci-
fied address to the logical ‘ 1 ’ state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed program-
low (T CSL ). DO at logical ‘ 0 ’ indicates that programming
is still in progress. DO at logical ‘ 1 ’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
ming cycle, except on ‘93C’ devices where the rising
edge of CLK before the last address bit initiates the
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
write cycle.
FIGURE 2-1:
CS
CLK
the Ready/ Busy status from DO.
ERASE TIMING FOR 93AA AND 93LC DEVICES
T CSL
Check Status
DI
1
1
1
A N
A N -1 A N -2
???
A0
T SV
T CZ
DO
High-Z
Busy
Ready
High-Z
T WC
FIGURE 2-2:
ERASE TIMING FOR 93C DEVICES
T CSL
CS
CLK
Check Status
DI
1
1
1
A N
A N -1 A N -2
???
A0
T SV
T CZ
DO
High-Z
Busy
Ready
High-Z
T WC
? 2003-2011 Microchip Technology Inc.
DS21794G-page 7
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